1. Field of the Invention
This application relates to memory circuits and systems, memory controller circuits and systems and memory testing circuits and systems, and, more particularly, to memory circuits and systems, memory controller circuits and systems and memory testing circuits and systems in which skew among multiple communication channels is substantially reduced or eliminated.
2. Description of the Related Art
In the fabrication of memory circuits and devices, it is necessary to test the memory circuit or device. This is typically accomplished using automatic test equipment (ATE) coupled to the memory circuit or device, i.e., the device under test (DUT). The ATE generates and transmits certain predetermined test signals to the DUT and receives response signals from the DUT and evaluates the DUT based on the responses.
FIG. 1 is a schematic block diagram of a typical test system 10. The test system 10 includes the ATE 12 and the DUT 14. Because of the high speed and complexity of memory circuits, the ATE 12 typically does not interface directly with the memory circuit DUT 14. A specialized test circuit 16 is typically interposed between the ATE 12 and the DUT 14. The test circuit 16 operates under the control of the ATE 12 to format test signals, forward the test signals to the DUT 14, receive the response signals from the DUT 14 and generate and forward test result information to the ATE 12. The test circuit 16 can be referred to as a built-off-test chip (BOT), meaning that it can be configured as a separate circuit off of the chip of the memory circuit DUT 14 and separated from the ATE 12.
The test circuit 16 communicates with the DUT over an interface 18, which includes a plurality of channels, generically identified by 20a, 20b, 20c, . . . , 20n. The test control signals, test data, DUT response signals, etc., used in testing the DUT 14 are transferred back-and-forth over the interface 18.
Due to variation in actual or effective length of the channels 20a, 20b, 20c 20d, signal propagation times among the channels are different. This “skew” in the propagation times can introduce errors in the process of testing the DUT. This is especially true in high-speed memory circuits, such as DDR3 DRAM memory circuits. In fact, at such high-speed operation, because of the channel skew, the control and data signals transferred between the test circuit 16 and the DUT 14 may not satisfy the specified DDR3 control and data signal requirements, making testing of the DDR3 memory circuit difficult or impossible.